Intel CPUs: Information Disclosure in Intel Processors via transient microarchitectural exposure (CVE-2024-28956) (CVE-2024-28956) #shorts

Summary

Today’s episode covers CVE-2024-28956, an information disclosure vulnerability in multiple Intel processors. Published on May 13, 2025, this flaw allows an authenticated local user to exploit shared microarchitectural structures during transient execution to leak sensitive data. While no public exploit exists, Intel and SUSE recommend applying microcode updates immediately.

Product details

CVE-2024-28956 affects a range of Intel processors; exact models are listed in Intel’s official references. The issue is addressed by updated CPU microcode provided by Intel and packaged in SUSE’s microcode_ctl utility. System administrators running SUSE Linux should install the latest ucode-intel package to mitigate the risk.

Vulnerability type summary

This is an information disclosure vulnerability arising from exposure of sensitive information in shared microarchitectural structures during transient execution. In plain terms, it’s a Spectre-class side-channel flaw where speculative or out-of-order CPU operations can leak data across trust boundaries.

Details of the vulnerability

An attacker with valid local credentials can trigger transient execution paths that leave remnant state in caches or other CPU buffers. By carefully measuring timing differences, the attacker can reconstruct sensitive information belonging to other processes or kernel memory. No remote attack vector exists; physical or remote console access with user privileges is required. Intel’s microcode update and SUSE’s microcode_ctl patch close the speculative execution window and prevent data leakage.

Conclusion

CVE-2024-28956 reinforces the need for timely microcode and OS patches to defend against speculative execution side-channel attacks. Although there’s no known exploit in the wild, administrators should apply Intel’s latest microcode and update SUSE’s ucode-intel package immediately. Stay vigilant and subscribe for updates on emerging processor vulnerabilities and mitigation best practices.

Watch the full video on YouTube: CVE-2024-28956

Remediation and exploitation details

This chain involves the following actors

  • Local Authenticated User: Potential attacker with legitimate login privileges
  • System Administrator: Responsible for securing systems and deploying updates
  • Intel Vendor Support: Provider of microcode patches and guidance

This following systems are involved

  • Intel Processor (Executes instructions and performs speculative execution): Contains shared microarchitectural buffers and caches
  • Operating System Kernel (Manages hardware resources and process isolation): Delivers microcode updates and enforces privilege boundaries
  • Microcode Update Service (Installs updated processor microcode): Applies firmware-level fixes inside the processor

Attack entry point

  • Local Login Session: Authenticated shell or user‐level session on the target machine
  • Transient Execution Path: Speculative execution mechanism within the processor that can leave traces in internal buffers
  • Shared Microarchitectural Structures: Caches and internal buffers that may reveal transient data through side channels

Remediation actions

System Administrator
Install the latest microcode update supplied by Intel
Microcode Update Service
System Administrator
Apply operating system kernel patches that enable new mitigations
Operating System Kernel
Intel Vendor Support
Provide updated firmware guidance and ensure compatibility with existing deployments
Intel Processor

Exploitation actions

Transient execution trigger

Local Authenticated User
Prepare user‐space code to drive speculative execution through indirect branch or out‐of‐bounds memory access
Intel Processor
Examples:
  • Write a loop that forces the processor to speculate past boundary checks

Cache eviction

Local Authenticated User
Flush selected cache lines corresponding to secret‐dependent memory locations
Intel Processor
Examples:
  • Use cache flush instructions to evict lines before triggering the transient read

Transient read

Local Authenticated User
Invoke the speculative code path that transiently reads secret data into a cache line
Intel Processor
Examples:
  • Access an index computed from secret bytes so that corresponding cache line is loaded speculatively

Cache timing side channel

Local Authenticated User
Measure reload times for each candidate cache line to identify which one was loaded
Intel Processor
Examples:
  • Time memory reads to each slot of a probe array to detect the one with low latency

Statistical analysis

Local Authenticated User
Aggregate timing results and reconstruct sensitive data from the timing patterns
Operating System Kernel
Examples:
  • Combine multiple measurements to recover key material or passwords

Related Content

NOTE: The following related content has not been vetted and may be unsafe.

CVE database technical details

CVE ID
CVE-2024-28956
Description
Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution for some Intel(R) Processors may allow an authenticated user to potentially enable information disclosure via local access.
Provider
intel
CWE / problem types
Information Disclosure,Exposure of Sensitive Information in Shared Microarchitectural Structures during Transient Execution
Affected Software Versions
n/a:Intel(R) Processors:[{'version': 'See references', 'status': 'affected'}]
Date Published
2025-05-13T21:02:56.170Z
Last Updated
2025-05-14T14:43:48.581Z